About Me

I am a professor in computer science at ENSTA-Bretagne, an engineering school located in Brest, France, where I serve as assistant head of research delegate to cyber security activities. I am also member of LabSticc , a major research laboratory in France.

My interest goes to designing CAD tools for either Reconfigurable Architectures such as FPGAs or non conventional architectures such as NASICs. I rely on pure object oriented languages such as Smalltalk to capture this domain and produce some quality software. My other interest is in cyber security and is related to designing evaluation tools dedicated to homomorphic encryption, and taking advantage of accelerated hardware (e.g reconfigurable extensions to RISC-V) to monitor systems.

CAD Tools for FPGA Madeo, Biniou, Drage, Argen are some innovative environments for FPGAs

Homomorphic Encryption schemes PAnThers is an environment that offers some evaluation facilities for homomorphic schemes

Smalltalk Language I rely on Visualworks & Pharo for my developments, and I'm involved in ESUG/IWST

Hardware support for Cyber security I'm interested in offering advanced monitoring capabilities in hardware as well as dedicated computing resources

Managerial responsibilities

From 2015 to 2017, I have served as the head of the STIC (Science, Technology, Information, Communication) department.

Since 2015, I jointly animate the CPER Cyber-SSI project with Frédéric Cuppens

Since 2017 I am the assistant to head of reseach at Ensta bretagne, in charge of cyber security

Journal publications

2020
• Nabil Kadjouh, Ahcène Bounceur, Madani Bezoui, Mohamed Essaid Khanouche, Reinhardt Euler, et al.. A Dominating Tree Based Leader Election Algorithm for Smart Cities IoT Infrastructure. Mobile Networks and Applications, Springer Verlag, 2020, ⟨10.1007/s11036-020-01599-z⟩. ⟨hal-02924057⟩
• Cyrielle Feron, Loïc Lagadec, Vianney Lapotre. Automated Exploration of Homomorphic Encryption Scheme Input Parameters  . Journal of Information Security and Applications, 2020, 55, pp.102627. ⟨10.1016/j.jisa.2020.102627⟩. ⟨hal-02960569v2⟩

2019
• Ahcène Bounceur, Madani Bezoui, Mohammad Hammoudeh, Loïc Lagadec, Reinhardt Euler. Finding the polygon hull of a network without conditions on the starting vertex. Transactions on emerging telecommunications technologies, Wiley-Blackwell, In press, pp.e3696. ⟨10.1002/ett.3696⟩. ⟨hal-02303242⟩

2017
• Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec. A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2016
• Mohamad Najem, Théotime Bollengier, Jean-Christophe Le Lann, Loïc Lagadec. Extended overlay architectures for heterogeneous FPGA cluster management. in Journal of System Architecture.
• Youenn Corre, Jean-Philippe Diguet, Dominique Heller, Dominique Blouin, Loïc Lagadec. TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA . in ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (1)

2014
• Loïc Lagadec, Ciprian Teodorov, Jean-Christophe Le Lann, Damien Picard, Erwan Fabiani. Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging. in Science of Computer Programming, 16 (1)

2013
• Ciprian Teodorov, Loic Lagadec, Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse, in Journal of Software: Pratice and Experience

2011
• Loïc Lagadec, Damien Picard, Youenn Corre, Pierre-Yves Lucas. Experiment Centric Teaching for Reconfigurable Processors, in International Journal of Reconfigurable Computing

2009
• Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz. Towards a Framework for Designing Applications onto hybrid nano/CMOS fabrics, in Microelectronics Journal, 40 (4-5)
• Loïc Lagadec, Bernard Pottier, Damien Picard. Toolset for Nano Reconfigurable Computing in in Microelectronics Journal, 40 (4-5)
• Damien Picard, Loïc Lagadec. Multilevel Simulation of Heterogeneous Reconfigurable Platforms, in International Journal of Reconfigurable Computingi
• Loïc Lagadec, Damien Picard, Bernard Pottier. Spatial Design. Book chapter in Dynamic System Reconfiguration in Lecture Notes in Electrical Engineering (40), Springer

2003
• Loïc Lagadec, Bernard Pottier, and Oscar Villellas-Guillen. An LUT-Based High Level Synthesis Framework for Reconfigurable Architectures. Book chapter in Domain-Specific Processors: Systems, Architectures, Modeling and Simulation. in CRC Press

Editing Activities

2020
• Loïc Lagadec, Anne Etien, Jannik Laval. Advances in Smalltalk technologies. Science of Computer Programming, Elsevier, 2020, 199, pp.102518. ⟨10.1016/j.scico.2020.102518⟩. ⟨hal-02960557⟩
2014
• Loïc Lagadec, Alain Plantec. Special issues on advances in smalltalk technologies, in Science of Computer Programming in Science of Computer Programming
e Alain Plantec, Loïc Lagadec. Special issue on international workshop on Smalltalk Technologies 2011, in Journal of Software: Practice and Experience.

2013
• Loïc Lagadec, Sébastien Pillement, Arnaud Tisserand. Architecture des ordinateurs, in Technique et Science Informatiques (TSI).

2011
• Michael Hübner, Jurgen Becker, Loic Lagadec, Gilles Sassatelli. Selected Papers from the International Workshop on Reconfigurable Communication-centric Systems on Chips, in International Journal of Reconfigurable Computing

Funded Research

DGA

• Overlays for long time maintenances 2014-2016
• Secure Overlays 2017-2020

Région Bretagne CPER 2015-2020

The Cyber-SSI project has been supported within the framework of the Brittany 2015-2020 State-Region Contract (CPER) by:
• the French Directorate General of Armaments (DGA),
• the European Regional Development Fund (ERDF) of the European Union,
• the Brittany Region (France),
• the Departmental Council of Finistere and
• Brest Metropole

ANR ARDyT 2011-2015 (site)

• Fault tolerant and self-adaptable dynamically reconfigurable embedded architecture with specific support mechanisms for the management of reliability
• Study and implementation of the reconfigurable hardware with integrated resources for improving testability and physical diagnosis of the circuit
• Definition and development of a set of design tools for synthesis, placement and routing dedicated to the proposed architecture
• Definition of test and tolerance methodologies adapted to dynamic architectures and using the intrinsic properties of the proposed platform

FP6 Morpheus 2008-2010 (Book)

• Design of a fully dynamically reconfigurable heterogeneous architecture
• ...downto a concrete SoC
• ...along with a complete compilation/synthesis toolchain

RNTL OSGAR 2003-2005

• Generic High-Level Synthesis for Reconfigurable Circuits

ST Central R&D 1999

• Low power partialy reconfigurable architecture
• Tool flow for prototype reconfigurable architecture
• Floorplanner, Place & Route, Editor, Metrics

Visitors