Input C code is:
unsigned short int sad4(unsigned char p1, unsigned char p2){ short int sub0a, sub1a, sub0b, sub1b; unsigned short int sub0, sub1; unsigned char cond0, cond1; unsigned char p10, p11, p20, p21; p10=p1; p11=p1 << 8; p20=p2; p21=p2 << 8; sub0a=p10 - p20; sub0b=p20 - p10; cond0=sub0a < 0; sub0=cond0 ? sub0b : sub0a; sub1a=p11 - p21; sub1b=p21 - p11; cond1=sub1a < 0; sub1=cond1 ? sub1b : sub1a; return(sub0 + sub1); } |
Resulting smalltalk code is:
sad4p1: p1 p2: p2 | sub0a sub1a sub0b sub1b sub0 sub1 cond0 cond1 p10 p11 p20 p21 | p10 := p1. p11 := p1 bitShift: 8. p20 := p2. p21 := p2 bitShift: 8. sub0a := p10-p20. sub0b := p20-p10. cond0 := sub0a<0. sub0 := cond0 ifTrue:[sub0b] ifFalse:[sub0a]. sub1a := p11-p21. sub1b := p21-p11. cond1 := sub1a<0. sub1 := cond1 ifTrue:[sub1b] ifFalse:[sub1a]. ^sub0+sub1. |
This code has been compiled in VisualWorks and given as input of the Madeo's synthesizer. Variables' types declared in C code are preserved in a symbol table and aim at being used for creating type contexts in Madeo FET.
DFG produced by Madeo:
High Level LUTS are produced after inference. As an example the following table isthe lut associated to the the first condition:
Based on these luts, and after a proper encoding is applied, blif (logic) files can be outputed:
The graph of blif files is floorplanned:
The place and route stage takes place to produce a full layout: