Madeo

Madeo FET

The Madeo framework [bib] [tutorial] [flyer] [doc] is an open and extensible modeling environment that allows to represent reconfigurable architectures. It acts as a one-stop shopping point providing basic functionalities to the programmer (place&route, floorplaning, simulation, etc.).

Madeo embeds a macro synthesizer that outputs BLIF files.

Setting up libraries of highly optimized operators is a time consuming task. Madeo-fet aims at decoupling behavioral specification from enumerated-types based contexts. The benefit is to support an automatic context-aware refactoring of operators.

[bib].

Applications for ﬁne grain reconﬁgurable architectures can be specialized without compromise, and they should be optimized in terms of space and performance. In our view, too much emphasis is placed on the local performance of standard arithmetic units in the synthesis tools and also in the speciﬁcation languages.
A ﬁrst consequence of this advantage is the restricted range of basic types coming from the capabilities of ALU/FPUs or memory address mechanisms. Control structures strictly oriented toward sequentiality are another aspect that can be criticized. As an example, programming for multimedia processor accelerators remains procedural in spite of all the experience available from the domain of data parallel languages. Hardware description languages have rich descriptive capabilities, however the necessity to use libraries has led the language designers to restrict their primitives to a level similar to C.

Madeo-FET aims to produce a more ﬂexible speciﬁcation level with direct and eﬃcient coupling to logic. This implies allowing easy creation of speciﬁc arithmetic representing the algorithm needs, letting the compilers automatically tune data width, and modeling computations based on well understood ob ject classes. The expected eﬀect is an easy production of dedicated support for processes that need a high level of availability, or could waste processor resources in an integrated system. To reach this goal, we use speciﬁcations with symbolic and functional characteristics, jointly with separate definition of data on which the program is to operate. Sequential computations can be structured in various ways by splitting programs on register transfers, either explicitly in the case of an architecture description, or implicitly during the compilation.

Textual editor

Floating point graph

(1) Floating point multiplication

The resulting graph is converted into logic by calling SIS.Yellow nodes are hierarchical ones, red nodes are atomic ones, red inputs are litterals (in this case, ArrayedResult class). The normalize:significand: node has been refactored and outputs two values: (value + offet).

Floating point minimizing

(2) Context aware optimization of (1)

Floating point multiplication after optimization process

(3) High level LUT representation of computations

Madeo offers a schematic view in addition to high level code based representation.
The application can be automatically implemented on reconfigurable architectures using MADEO-Fet, as illustrated by (4) and (5).

Floating point circuit (hieraarchical)

(4) Hierarchical circuit

Floating point circuit (flatten)

(5) Flatten circuit

More complex cases have been considered in the scope of the VALMADEO project. Also tracing techniques can substitute to enumeration in order to simply the whole process depending on the
application context.

Madeo

Madeo FET

Social networks

Coming to Ensta Bretagne